In a semiconductor device to be loaded on a vehicle, such as a microcomputer for controlling the vehicle engine used in a high noise environment, the first priority should be given to the withstand voltage despite some disadvantages therefore, such as the slight degradation of the integration degree or an increase in the number of manufacturing processes. This purpose is most suitably served by a transistor integrated circuit of side dielectric isolation structure or total (side and bottom) dielectric isolation structure (as disclosed in the Japanese Unexamined Patent Publication No. 48-100081).
An example of high withstand voltage type NPN bipolar transistors of total dielectric isolation structure is illustrated in FIG. 27. In this figure, reference number 3 denotes a buried collector region; 101, a low concentration collector withstand voltage region; 102, a high concentration base region; 103, an emitter region; 100, a bottom dielectric isolation oxide film; and 104, a side dielectric isolation oxide film.
In this bipolar transistor, as a high voltage is applied to between the base region 102 and the buried collector region 3, a base/collector junction J is subjected to a strong reverse bias, and a depletion layer DL (not illustrated) thereof greatly extends into the collector withstand voltage region 101 engulfing the base region 102.
In the high withstand voltage semiconductor device of the above structure, it is so designed that depletion layer DL in the base/collector junction J can not reach the buried collector region 3. Similarly, it is also designed so that the base region 102 is sufficiently separated from the side dielectric isolation oxide film 104 so as not to allow the depletion layer DL to reach the side isolation oxide film 104.
The depletion layer DL in the base/collector junction J is designed so as to be separated from the buried collector region 3. One of the reasons for this arrangement in design is that the contact of the depletion layer DL in the base/collector junction J (corresponding to the gate/drain junction of power MOSFET) with the buried collector region 3 (corresponding to the drain area of power MOSFET) would have an effect on the collector current due to a change in the collector voltage when the transistor is switched ON.
Another reason for the above design arrangement is that an increase in the reverse bias voltage between the base and the collector after the arrival of the depletion layer DL in the buried collector region would allow the depletion layer DL to extend to the base side, causing an increase in the base resistance, i.e., leading to a change in the electric characteristics and ending up in a punch through phenomena between the emitter and the collector.
On the other hand, the depletion layer DL in the base/collector junction J is designed so as to be separated from the side dielectric isolation oxide film 104. One of the reasons for this design arrangement is that the formation of a transistor similar to the above transistor in a conduction region (not illustrated) which is in contact with the depletion layer DL through the side dielectric isolation oxide film 104 would cause the withstand voltage characteristics of the transistor to be degraded due to the effect of the electric potential at the conductive region on the profile of the depletion layer DL.
Nevertheless, higher withstand voltage performance is required for the above conventional high withstand transistor.
Of course, the lower the concentration of impurities in the collector withstand voltage region 101 is, the wider the depletion layer DL is, and the higher the withstand voltage performance is. However, in order to prevent the extension of the depletion layer DL to the side dielectric isolation oxide film 104 and/or the buried collector region 3 due to the expansion of the depletion layer DL, the collector withstand voltage region 101 should be expanded in lateral width and depth. The increase in the lateral width and depth of the collector withstand voltage region 101, however, would degrade the integration degree of the transistor.
In view of the above, it is an object of the present invention to provide an semiconductor device which can compatibly improve both the withstand voltage performance and the integration degree.